The present invention relates to a matrix type image display device having a structure for stabilizing the operation of a shift register that transfers a digital signal in synchronism with a clock signal, more particularly a structure for preventing an operational error due to indefiniteness of an internal state when power is supplied.
The present invention is directed to various image display devices. Here, the present invention is explained by particularly illustrating an active matrix type liquid crystal display device as an example. However, the present invention is not necessarily limited to this example, and is applicable to devices and systems in other fields for the same purposes.
A known conventional image display device is an active matrix drive-type liquid crystal display device. As shown in FIG. 43, this liquid crystal display device includes a pixel array 101, a scanning signal line drive circuit 102, a data signal line drive circuit 103, a pre-charge circuit 104, and a control circuit 105.
The pixel array 101 includes a number of scanning signal lines GL (GLj, GLj+1, . . . ) and data signal lines SL (SLj, SLj+1, . . . ) that cross each other, and pixels 101a (shown as PIX in FIG. 43) arranged in a matrix form. As shown in FIG. 5, the pixel 101a is composed of a pixel transistor SW as a switching element and a pixel capacitor CP including a liquid crystal capacitor CL (and a storage capacitor CS, if necessary).
The data signal line drive circuit 103 samples an input image signal DAT (data) in synchronism with a control signal such as a clock signal SCK, amplifies it, if necessary, and outputs the resultant signal to each data signal line SL. The scanning signal line drive circuit 102 sequentially selects scanning signal lines GL in synchronism with a control signal such as a clock signal GCK and controls the opening and closing of the pixel transistor SW in the pixel 101a so as to write and hold in each pixel 101a the image signal DAT output to each data signal line SL. The pre-charge circuit 104 is a circuit provided, if necessary, to support the output of the image signal to the data signal lines SL, and preliminarily charges the data signal lines SL before outputting the image signal DAT from the data signal line drive circuit 103 to the data signal lines SL.
By the way, in the conventional active matrix type liquid crystal display device as described above, an amorphous silicon thin film formed on a transparent substrate such as a glass substrate is used as a material of the pixel transistor SW. Besides, the scanning signal line drive circuit 102 and data signal line drive circuit 103 are formed by external integrated circuits (IC) respectively.
On the other hand, in recent years, in order to meet demands for an improvement of the driving force of the pixel transistor SW for an increase in the size of the screen, a reduction of the mounting cost of the drive ICs and the mounting reliability, a technique for fabricating the pixel array 101 and drive circuits 102 and 103 in a monolithic form by the use of a polycrystalline silicon thin film was developed and reported. Moreover, in order to further increase the size of the screen and reduce the cost, attempts to form the pixel array 101 and drive circuits 102 and 103 by a polycrystalline silicon thin film on the glass substrate at a process temperature of not higher than a distortion point (about 600xc2x0 C.) of glass have been made.
For example, a liquid crystal display device shown in FIG. 44 employs a structure in which the pixel array 101, scanning signal line drive circuit 102 and data signal line drive circuit 103 are mounted on a glass substrate 107, and the control circuit 105 and power supply circuit 106 are connected to them.
Next, the structure of the data signal line drive circuit 103 will be explained. As the data signal line drive circuit 103, a dot sequential driving-type and line sequential driving-type used according to the type of an input signal have been known. In general, in a polycrystalline silicon TFT panel in which the drive circuits and pixels are formed to be monolithic, a point sequential driving-type drive circuit is often used because of the simpleness of the circuit structure. Therefore, the dot sequential driving-type scanning signal line drive circuit 102 and data signal line drive circuit 103 will be described here.
For example, as shown in FIG. 45, the dot sequential driving-type data signal line drive circuit 103 includes a shift register 111 for sequentially transferring a start signal SST at the timing of the clock signal SCK and inverted clock signal /SCK (the inverted signal of SCK). In this data signal line drive circuit 103, the result of a logical operation of output pulses of adjacent two flip-flops 111a in the shift register 111 is obtained by, for example, a NAND gate 111c, and an output pulse of the NAND gate 111c that has passed through the buffer circuit 112 is supplied as a control signal for a sampling switch 113. The sampling switch 113 fetches the input image signal DAT and outputs it to the data signal lines SLn (n=1, 2, 3, 4, . . . ) when it is turned on by the control signal.
However, the logic circuit such as the NAND gate 111c is provided, if necessary. In other words, if the logical operation is not necessary, the image signal DAT is sampled according to the output pulse of the flip-flop 111a. 
As shown in FIG. 46, the scanning signal line drive circuit 102 includes a shift register 111 for sequentially transferring a start signal GST at the timing of the clock signal GCK and inverted clock signal /GCK (the inverted signal of GCK). In this scanning signal line drive circuit 102, the result of a logical operation of output signals of adjacent two flip-flops 111a in the shift register 111 is obtained by, for example, a NAND gate 111c, and a scanning signal is obtained. More specifically, the result of a logical operation of the output pulse of the NAND gate 111c and an inverted signal /GEN of an enable signal GEN supplied from the control circuit 105 is obtained by, for example, a NOR gate 114, and the result is output as a scanning signal via a buffer circuit 115 to the scanning signal lines GLn (n=1, 2, 3, 4, . . . ).
However, if the logical operation is not necessary, the output of the flip-flop 111a is used as a scanning signal.
As described above, in both of the data signal line drive circuit 103 and scanning signal line drive circuit 102, the shift register 111 for sequentially transferring a pulse signal is used. This shift register 111 employs a structure in which a plurality of flip-flops 111a are connected in series, and is driven by the clock signal SCK, inverted clock signal /SCK, clock signal GCK and inverted clock signal /GCK as shown, for example, in FIGS. 45 and 46.
The flip-flop shown in FIG. 47 is composed of one inverter 121 and two clocked inverters 122 and 123. The clock signal CK and inverted clock signal /CK input to the two clocked inverters 122 and 123 have opposite phases. In adjacent flip-flops, the input clock signals have opposite phases. In general, this type of flip-flop is referred to as a D-type flip-flop.
For example, as shown in FIG. 48, other data signal line drive circuit 103 is formed by an S-R flip-flop 111b which is driven by a set signal for causing the inside to be an active state and a reset signal for causing the inside to be an inactive state.
As shown in FIGS. 48 and 49, in an S-R flip-flop 111b, the inverted clock signal /CK (/SCK) input according to the control by an output signal G of the flip-flop 111b in the preceding stage is used as the set signal, and the output signal of the flip-flop 111b in the succeeding stage is used as the reset signal RES. The clock signals of opposite phases are input to adjacent flip-flops 111b, respectively. In this flip-flop 111b, the inverted clock signal /SCK is used as the inverted clock signal /CK.
In this flip-flop 111b, when the active inverted clock signal /CK is input via an N-channel transistor 131 which was turned on by the output signal G, a P-channel transistor 132 is turned on, while N-channel transistors 133 and 134 are turned off. In this case, therefore, a signal of power supply level is output via inverters 135 and 136. Besides, when the set signal becomes inactive and the reset signal RES becomes active, the N-channel transistors 133 and 137 are turned on, while a P-channel transistor 138 is turned off. Consequently, a signal of ground level is output via the inverters 135 and 136.
By the way, in the shift register 111 for use in the above-mentioned data signal line drive circuit 103 (see FIGS. 45 and 48), since the clock signal SCK and inverted clock signal /SCK are input to all of the flip-flops 111a or 111b, the load capacity of the clock signal line is extremely large. Therefore, it is necessary to use an IC of a great drive ability as an external IC such as a controller IC including therein a control circuit 105 for driving the clock signal line. For this reason, not only the cost is increased, but also the power consumption is increased.
On the other hand, Japanese laid-open patent publication (Tokukaihei) No. 3-147598 (published date: Jun. 24, 1991) discloses a structure in which, in order to reduce the load capacity of the clock signal line, only when the output of each stage (flip-flop) in the shift register is valid (in an active state), the clock signal is input to the flip-flop. More specifically, in this shift register, whether the clock signal is connected to or disconnected from each flip-flop is controlled by the output signal of each flip-flop or a logical combination signal of the output signals of a plurality of adjacent flip-flops.
However, in such a structure, the initial state (voltage level) of the internal node of the shift register is indefinite and may turn into any condition when the power is supplied. In the worst case, all of the internal nodes of the shift register turn into an active state upon the supply of power. This condition continues until a signal corresponding to the inactive state scans the entire shift register so as to initialize the shift register.
In this condition, since the clock signal is input to all of the flip-flops, the load capacity of the clock signal line is extremely large compared with that in a normal condition (a condition in which one pulse signal is scanned in a shift register in which the number of the flip-flops to which the clock signal is input is limited to one or several flip-flops). Thus, if the external IC does not have a sufficient drive ability optimized for a small load capacity, there is a possibility that the clock signal line can not be driven within a predetermined time and the shift register can not be operated.
As described above, in the structure (see FIG. 44) in which the pixel array and the drive circuits are fabricated in a monolithic form on a single glass substrate, there is a tendency to reduce the input voltage (amplitude) in the drive circuit for the purpose of reducing the power consumption and increasing the operation speed like the recent IC. Moreover, in order to simplify the input interface, it is necessary to reduce the amplitude of the input voltage. However, in the drive circuit, in order to obtain a predetermined drive ability, it is necessary to use a higher voltage than the input voltage. Hence, by including a booster circuit (level shift circuit) in each of the flip-flops constituting the shift register, the input voltage is raised.
Here, when a current-driven type level shift circuit is used to increase the operation margin of the level shift circuit, since the transistor in the input stage is always turned on during the operation, a steady-state current flows. For this reason, when a number of nodes in the shift register become active, not only the consumption current becomes extremely large, but also a voltage drop occurs. Thus, there is a possibility that errors occur in the succeeding operation.
It is thus necessary to reset the internal nodes (the output of each flip-flop) of the shift register when the power is supplied. However, if the reset signal is supplied from an external device, not only the number of terminals for inputting the reset signal to a liquid crystal display element in which the drive circuits are mounted is increased, but also the load of the control circuit (controller) is increased.
It is an object of the present invention is to provide a matrix type image display device which includes a shift register as a part of a drive circuit, and is capable of resetting the internal nodes of the shift register without inputting a reset signal from an external device and capable of reducing the power consumption and cost.
In order to achieve the above object, a first matrix type image display device of the present invention, which is a matrix type image display device including a plurality of pixels arranged in a matrix form; a plurality of data signal lines for supplying image data to be written in the pixels; a plurality of scanning signal lines for controlling writing of the image data in the pixels; a data signal line drive circuit for driving the data signal lines; a scanning signal line drive circuit for driving the scanning signal lines; reset means for resetting an internal state of at least one of the data signal line drive circuit and the scanning signal line drive circuit; and a shift register as a part of the data signal line drive circuit and the scanning signal line drive circuit, is characterized in that the reset means generates a reset signal for resetting the internal state of the shift register that forms at least one of the data signal line drive circuit and the scanning signal line drive circuit, based on a combination of a plurality of signals which are not used during normal driving.
In this structure, since the reset means generates a reset signal based on a specific combination of signals as mentioned above, the shift register provided in the data signal line drive circuit and the scanning signal line drive circuit is reset (the internal nodes are made inactive) by the use of this reset signal. Hence, it is possible to prevent an indefinite state when power is supplied. Moreover, in order to generate the reset signal, it is possible to use existent signals generated in an external control circuit such as a controller. Therefore, if the reset means is provided in the succeeding stage of an input terminal for inputting these signals, it is not necessary to additionally provide an input terminal for the reset signal. It is thus possible to limit the increase in the scale of the external control circuit and the increase in the number of terminals.
In order to achieve the above object, a second matrix type image display device of the present invention, which is a matrix type image display device including a plurality of pixels arranged in a matrix form; a plurality of data signal lines for supplying image data to be written in the pixels; a plurality of scanning signal lines for controlling writing of the image data in the pixels; a data signal line drive circuit for driving the data signal lines; a scanning signal line drive circuit for driving the scanning signal lines; reset means for resetting an internal state of at least one of the data signal line drive circuit and the scanning signal line drive circuit; and a shift register as a part of the data signal line drive circuit and the scanning signal line drive circuit, is characterized in that the reset means generates a reset signal for resetting the internal state of the shift register that forms at least one of the data signal line drive circuit and the scanning signal line drive circuit, based on a combination of a plurality of signals which do not affect a displayed image.
In this structure, examples of a combination of signals which does not affect the displayed image include a combination of signals generated in a period other than an image display period, such as a flyback period, and a combination of signals related to a circuit which is not used for display even in the display period. With the use of such a combination of signals, it is possible to reset the internal state of the shift register without affecting the image display, thereby avoiding an indefinite state when power is supplied.
In order to achieve the above object, a third matrix type image display device, which is a matrix type image display device including a plurality of pixels formed in a matrix form on a single substrate; a plurality of data signal lines for supplying image data to be written in the pixels; a plurality of scanning signal lines for controlling writing of the image data in the pixels; a data signal line drive circuit for driving the data signal lines according to a signal input from outside of the substrate; a scanning signal line drive circuit for driving the scanning signal lines according to signals input from outside of the substrate; a pre-charge circuit for preliminarily charging the data signal lines before being driven, according to signals input from outside of the substrate; reset means for resetting an internal state of at least one of the data signal line drive circuit and the scanning signal line drive circuit; and a shift register as a part of the data signal line drive circuit and the scanning signal line drive circuit, is characterized in that at least one of the data signal line drive circuit, scanning signal line drive circuit and pre-charge circuit is formed on the substrate on which the pixels are formed, and the reset means generates a reset signal for resetting the internal state of the shift register that forms at least one of the data signal line drive circuit and the scanning signal line drive circuit, based on a combination of a plurality of signals which are input from outside of the substrate to at least one of the data signal line drive circuit, scanning signal line drive circuit and pre-charge circuit formed on the substrate.
According to this structure, a reset signal for resetting the internal state of the shift register that forms at least one of the data signal line drive circuit and the scanning signal line drive circuit is generated based on a combination of a plurality of signals which are input from outside of the substrate to at least one of the data signal line drive circuit, scanning signal line drive circuit and pre-charge circuit formed on the substrate. Therefore, in order to reset the internal state of the shift register, it is not necessary to supply the reset signal from outside of the substrate to the circuits on the substrate independently of a signal input to the circuits (data signal line drive circuit, scanning signal line drive circuit and pre-charge circuit) on the substrate from outside of the substrate. It is thus possible to reduce the number of signals supplied to the circuits on the substrate from outside of the substrate.
As a result, the number of signal lines for supplying signals to the circuits on the substrate from outside of the substrate can be decreased, thereby reducing the cost and size of the device. Moreover, it is not necessary to improve the drive ability of the external IC for supplying signals to the circuits on the substrate from outside of the substrate and the supply ability of a power supply circuit, and consequently the cost and power consumption of the external IC can be reduced.
Furthermore, in the third matrix type image display device, at least one of the data signal line drive circuit, scanning signal line drive circuit and pre-charge circuit is formed on the substrate on which the pixels are formed, and therefore at least one of the data signal line drive circuit, scanning signal line drive circuit and pre-charge circuit can be formed on the substrate on which the pixels are to be formed by a single process.
In order to achieve the above object, a fourth matrix type image display device, which is a matrix type image display device including a plurality of pixels formed in a matrix form on a single substrate; a plurality of data signal lines for supplying image data to be written in the pixels; a plurality of scanning signal lines for controlling writing of the image data in the pixels; a data signal line drive circuit for driving the data signal lines according to a signal input from outside of the substrate; a scanning signal line drive circuit for driving the scanning signal lines according to signals input from outside of the substrate; reset means for resetting an internal state of at least one of the data signal line drive circuit and the scanning signal line drive circuit; and a shift register as a part of the data signal line drive circuit and the scanning signal line drive circuit, is characterized in that at least one of the data signal line drive circuit and scanning signal line drive circuit is formed on the substrate on which the pixels are formed, and the reset means generates a reset signal for resetting the internal state of the shift register that forms at least one of the data signal line drive circuit and the scanning signal line drive circuit, based on a combination of a plurality of signals which are input from outside of the substrate to at least one of the data signal line drive circuit and scanning signal line drive circuit formed on the substrate.
According to this structure, a reset signal for resetting the internal state of the shift register that forms at least one of the data signal line drive circuit and the scanning signal line drive circuit is generated based on a combination of a plurality of signals which are input from outside of the substrate to at least one of the data signal line drive circuit and scanning signal line drive circuit formed on the substrate. Therefore, in order to reset the internal state of the shift register, it is not necessary to supply the reset signal from outside of the substrate to the circuits on the substrate independently of a signal input to the circuits (data signal line drive circuit and scanning signal line drive circuit) on the substrate from outside of the substrate. It is thus possible to reduce the number of signals supplied to the circuits on the substrate from outside of the substrate.
As a result, the number of signal lines for supplying signals to the circuits on the substrate from outside of the substrate can be decreased, thereby reducing the cost and size of the device. Moreover, it is not necessary to improve the drive ability of the external IC for supplying signals to the circuits on the substrate from outside of the substrate and the supply ability of a power supply circuit, and consequently the cost and power consumption of the external IC can be reduced.
Furthermore, in the fourth matrix type image display device, at least one of the data signal line drive circuit and scanning signal line drive circuit is formed on the substrate on which the pixels are formed, and therefore at least one of the data signal line drive circuit and scanning signal line drive circuit can be formed on the substrate on which the pixels are to be formed by a single process.
Incidentally, the reset means in the first to fourth matrix type image display devices can be formed by an arithmetic element for converting the polarities of a plurality of signals so as to match the data signal line drive circuit or scanning signal drive circuit and generating a reset signal based on a plurality of signals and resistors or capacitors for biasing at a fixed level, etc.
In order to achieve the above object, a fifth matrix type image display device of the present invention is characterized in that the reset means is capacitors which are added to internal nodes of the shift register that forms at least one of the data signal line drive circuit and the scanning signal line drive circuit, for resetting the internal nodes.
In this structure, since the shift register is initialized (reset) by using the capacitors when power is supplied, it is not necessary to provide a switch for initialization, thereby achieving a reduction in the circuit scale. Furthermore, it is not necessary to generate a signal for driving the initialization switch, thereby simplifying the circuit structure.
In order to achieve the above object, a sixth matrix type image display device of the present invention is characterized in that the reset means is resistors which are added to internal nodes of the shift register that forms at least one of the data signal line drive circuit and the scanning signal line drive circuit, for resetting the internal nodes.
In this structure, since the shift register is initialized (reset) by using the resistors when power is supplied, it is not necessary to provide a switch for initialization, thereby achieving a reduction in the circuit scale. Furthermore, it is not necessary to generate a signal for driving the initialization switch, thereby simplifying the circuit structure.
For a fuller understanding of the nature and advantages of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings.